XSM Instruction Set

Every instruction in XSM is 2 words long. The instructions provided by the XSM architecture can be classified into unprivileged (user) and privileged (kernel) instructions. The semantics of each instruction is different, depending on the mode in which the machine is running.

Unprivileged Instructions¶

XSM provides a set of unprivileged instructions, which are the only instructions available when the machine is executing in the user mode. The machine can execute unprivileged instructions in kernel mode also, however, the instruction semantics will be different as explained in Paging hardware. The unprivileged instructions are Data Transfer Instructions, Arithmetic Instructions, Logical Instructions, Stack Instructions, Sub-routine instructions, Debug instructions and Software interrupts. Registers available in user mode are R0-R19, SP, BP and IP.

[Data Transfer Instructions]¶

1. Register Addressing :¶

Syntax : MOV Ri, Rj
Semantics : Copies the contents of the register Rj to Ri.

2. Immediate Addressing :¶

Syntax : MOV Ri, INTEGER/STRING
Semantics : Copies the INTEGER/STRING to the register Ri.

3. Register Indirect Addressing:¶

Syntax : MOV Ri, [Rj]
Semantics : Copy contents of memory location pointed by Rj to register Ri.
Syntax : MOV [Ri], Rj
Semantics : Copy contents of Rj to the location whose address is in Ri.

4. Direct Addressing :¶

Syntax : MOV [LOC], Rj
Semantics : Copy contents of Rj to the memory address LOC.
Syntax : MOV Rj, [LOC]
Semantics : Copy contents of the memory location LOC to the register Rj.

For all the above instructions, Ri/Rj may be any register except IP.

[Arithmetic Instructions]¶

Arithmetic Instructions perform arithmetic operations on registers containing integers. If the register contains a non-integer value, an exception (illegal instruction) is raised.

1. ADD, SUB, MUL, DIV and MOD¶

Syntax : OP Ri, Rj
Semantics : The result of Ri op Rj is stored in Ri.
Syntax : OP Ri, INTEGER
Semantics : The result of Ri op INTEGER is stored in Ri.

2. INR, DCR¶

Syntax : OP Ri
Semantics : Increments/Decrements the value of register Ri by 1.

For all the above instructions, Ri/Rj may be any register except IP.

[Logical Instructions]¶

Logical instructions are used for comparing values in registers. Strings can also be compared according to the lexicographic ordering of ASCII. If one of the operands is a string, the other operand will also be considered as a string. The logical instructions are LT, GT, EQ, NE, GE and LE.

LT, GT, EQ, NE, GE, LE
Syntax : OP Ri, Rj
Semantics : Stores 1 in Ri if the value stored in Ri is less than/greater than/equal to/not equal to/greater than or equal to/less than or equal to that in Rj. Ri is set to 0 otherwise.

For all the above instructions, Ri/Rj may be any register except IP.

[Branching Instructions]¶

Branching is achieved by changing the value of the IP to the word address of the target instruction specified by 'target_address'.

1. JZ¶

Syntax : JZ Ri, target_address
Semantics : Jumps to target_address if the contents of Ri is zero.

2. JNZ¶

Syntax : JNZ Ri, target_address
Semantics : Jumps to target_address if the contents of Ri is not zero.

3. JMP¶

Syntax : JMP target_address
Semantics : Unconditional jump to target_address.

For all the above instructions, Ri/Rj may be any register except IP.

[Stack Instructions]¶

1. PUSH¶

Syntax : PUSH Ri
Semantics : Increment SP by 1 and copy contents of Ri to the location pointed to by SP.

2. POP¶

Syntax : POP Ri
Semantics : Copy contents of the location pointed to by SP into Ri and decrement SP by 1.

For all the above instructions, Ri/Rj may be any register except IP.

[Subroutine Instructions]¶

The CALL instruction copies the address of the next instruction to be fetched(this value must be IP + 2 since each instruction is two memory words) on to location SP + 1. It also increments SP by one and transfers control to the instruction specified by the target_address. The RET instruction restores the IP value stored at location pointed by SP, decrements SP by one and continues execution fetching the next instruction pointed to by IP.

1. CALL¶

Syntax : CALL target_address / Ri
Semantics : Increments SP by 1, transfers IP + 2 to location pointed to by SP and jumps to instruction specified by target_address/Ri.

For the CALL instruction, Ri/Rj may be any register except IP.

2. RET¶

Syntax : RET

Semantics : Sets IP to the value pointed to by SP and decrements SP.

[Debug Instruction]¶

Syntax : BRKP

Semantics : The machine when run in debug mode invokes the debugger when this intruction is executed. This instruction can be used for debugging system code.

[Software Interrupts]¶

Syntax : INT n

Semantics : Generates an interrupt to the kernel with n (4 to 18) as a parameter. This involves a change of mode from user to kernel mode. It also disables the interrupts. The Stack Pointer is first incremented, the physical address of SP is calculated and the (virtual) address of the next instruction after the current value of IP is stored into that location (See Address Translation). After this, the execution mode is switched to Kernel mode. Note that, INT can be invoked only from the User Mode. The IP value must contain a virtual address and hence, the value pushed into stack is a virtual address and not a physical address. Finally, the IP value is set according to the value of n as specified here.

[NOP Instruction]¶

Syntax : NOP

Semantics : Instruction that does nothing.

Privileged Instructions¶

Privileged instructions can be executed only in the kernel mode (both priviliged instructions and unpriviliged instructions can be executed in the kernel mode). It should be noted that all the addresses in the kernel mode should be physical addresses, whereas the user mode uses logical addresses, with address translation done using the Paging hardware. Privileged Instructions are:

[LOADI]¶

Syntax : LOADI pagenum blocknum

Semantics : This instruction loads the disk block specified by blocknum to the memory page specified by pagenum. Blocknum and pagenum should be numbers or registers containing numbers. The machine will wait for the disk transfer to complete and continue execution of the next instruction only after the block transfer is completed by the disk controller.

[LOAD]¶

Syntax : LOAD pagenum blocknum

Semantics : This instruction initiates the transfer of the disk block specified by blocknum to the memory page specified by pagenum, using the disk controller. Blocknum and pagenum should be numbers or registers containing numbers. The machine proceeds to execute the next instruction without waiting for the completion of the block transfer. The disk controller raises the disk interrupt when the transfer is completed.

[STORE]¶

Syntax : STORE pagenum blocknum

Semantics : This instruction initiates the transfer of the memory page specified by pagenum to the disk block specified by blocknum, using the disk controller. Blocknum and pagenum should be numbers or registers containing numbers. The machine proceeds to execute the next instruction without waiting for the completion of the block transfer. The disk controller raises the disk interrupt when the transfer is completed.

[ENCRYPT]¶

Syntax : ENCRYPT Ri

Semantics : This instruction replaces the value in the register Ri with its encrypted value. The details of the encryption scheme used is left unspecified.

[BACKUP]¶

Syntax : BACKUP

Semantics : This instruction is used to backup all the machine registers (except SP, IP, exception flag registers and ports) into the memory locations starting from the address pointed to by SP in the order : BP, R0 - R19. The value of SP gets incremented accordingly.

[RESTORE]¶

Syntax : RESTORE

Semantics : This instruction is used to restore the backed up machine registers from memory. The registers are restored from contiguous memory locations starting from the address pointed to by SP in the order : R19-R0, BP. The value of SP gets decremented accordingly.

[PORT]¶

Syntax : PORT Ri, Pj

Semantics : Transfers the contents of port Pj to register Ri.

Syntax : PORT Pi, Rj

Semantics : Transfers the contents of register Rj to port Pi.

[IN]¶

Syntax : IN

Semantics : IN initiates reading a word from the standard console. The machine proceeds to the execution of the next instruction without waiting for the console read to complete. When a word is read from the console, the console controller stores the word to the port P0 (which is reserved for the console input) and raises the console interrupt.

[INI]¶

Syntax : INI

Semantics : INI initiates reading a word from the standard console. This instruction gets enabled in the debug mode only. The machine waits for the console read to complete before proceeding to the execution of the next instruction. When a word is read from the console, the console controller stores the word to the port P0. Console interrupt is not raised here.

[OUT]¶

Syntax : OUT

Semantics : Transfers the contents of P1 to the standard output immediately.

[IRET]¶

Syntax : IRET

Semantics : This instruction is used to return control to a user mode program from an interrupt service routine/exception handler. This involves a change of mode from kernel to user mode. With the execution of the IRET instruction, interrupts are enabled. The address of the next instruction to be executed by the user program is popped from the stack and set to the IP Register, following which the Stack Pointer is decremented. Since the IP value must contain a virtual address while executing in User Mode, the value obtained from stack is treated as a virtual address and not a physical address (See Address Translation). Note that the machine switches to user mode just before the execution of the IRET instruction. Thus the address pointed to by SP is treated as a virtual address and the machine translates this address into physical address using the page translation scheme, before popping the IP value.

[HALT]¶

Syntax : HALT

Semantics : This instruction causes the machine to halt immediately.

NEXSM Additional Privileged Instructions¶

TSL¶

Syntax : TSL Rj, [loc]

Semantics : The contents of the memory location [loc] is copied to register Rj. The value of [loc] is set to 1. This instruction is atomic. That is, when one of the cores is executing the TSL instruction, the memory bus is locked to avoid the other processor from simultaneously accessing [loc].

START¶

Syntax : START

Semantics : If this instruction is executed by the primary while the machine is in reset mode, then secondary core starts parallel execution at the starting address of memory page 128 (physical address 65536). The START instruction is ignored if executed when the machine is in active mode.

RESET¶

Syntax : RESET

Semantics : The instruction, when executed in active mode sets the machine to reset mode. The instruction is ignored if executed in reset mode.